AI-native thermal physics for microelectronics
The first GPU-native multiscale non-Fourier thermal model, from transistor to chip, and the only one differentiable end-to-end to enable gradient-based design optimization.
Why Fourier breaks
Below the phonon mean free path, ballistic transport dominates and Fourier's law breaks down. Commercial EDA thermal tools — built on Fourier — can underpredict peak nano-transistor temperatures by up to 90 °C. They predict barely any heat up where the physics yields 124 °C. That's the difference between a chip that runs and a chip that fails.
Peak temperature, identical FinFET-array geometry. Difference: 90 K.
How it works
Three pillars work together so you get ground-truth phonon physics in the transistor, millisecond inference for design loops, and chip-scale assemblies in one continuous pipeline.
GPU-native FVM solver for the non-gray phonon Boltzmann Transport Equation. Discrete ordinates, BiCGSTAB inner solves, automatic differentiation end-to-end — forward and inverse, both.
FinNET and SOLDER — operator-learning surrogates trained on JAX-BTE ground truth. Millisecond inference at 95–99% BTE accuracy. Training in under 30 minutes on a single GPU.
Overlapping domain decomposition: BTE-accurate solves in transistor regions (Kn ≥ 1) coupled to Fourier solvers in substrate regions. 7× speedup, 74% memory reduction, sub-1 K error.
Interactive · 360,000 transistors
Drive in from a 360,000-transistor overview to the internal mechanics of a single FinFET. Drag the heat source slider to see the thermal field respond. Built on the same JAX-BTE-trained surrogates we ship to customers.
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Receipts
Published
Peer-reviewed validation in Nature Portfolio — convergence, FinFET arrays, inverse recovery, all benchmarked.
Read the paper ↗Patented
Tensor-based parallel BTE execution, differentiable inverse design, multiscale coupling — protected end-to-end.
Funded
Supported by DARPA Thermonat Program and the NSF FUSE2 Program.
Discovery
We talked to thermal engineers at the top foundries and the largest fabless designers. They told us where the gaps are.
3D IC thermo-mechanical modeling is a gold mine — there are no good existing models.
A differentiable thermal solver would be fantastic for design optimization. Current tools are impractical at optimization scale.
Reduced-order thermal models take two hours per chip. We'd value a tool like this in the tens of millions.
Quotes anonymized; pending permission for attribution.
Next steps
Benchmark JAX-BTE on your geometry. We'll run a head-to-head against your current Fourier tool.
Request a benchmark →
Talk to us about integration paths, OEM licensing, or co-development.
Discuss integration →
DARPA, NSF, Air Force, NRO — we brief on national-security-relevant thermal modeling.
Brief our team →
$14.5B EDA market growing to $26B by 2028. Patent-protected, single-GPU 100M DoF, multi-GPU scaling.
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